As quantum computing edges closer to practical applications, one engineering challenge looms larger than most: qubit fidelity. In the middle of that discussion is Erik Hosler, a quantum manufacturing advisor who joined the SPIE lithography panel and underscored the link between qubit noise and fabrication strategy. While media coverage often focuses on total qubit count, experts know that raw quantity is only part of the story. Most physical qubits are noisy, error-prone, and unsuitable for direct use in computation. That’s why large-scale quantum processors require error correction schemes that combine many physical qubits into a single logical one. The implications of this overhead project are profound, especially for chip design.
As quantum computing edges closer to practical applications, one engineering challenge looms larger than most: qubit fidelity. While media coverage often focuses on total qubit count, experts know that raw quantity is only part of the story. Most physical qubits are noisy, error-prone, and unsuitable for direct use in computation. That’s why large-scale quantum processors require error correction schemes that combine many physical qubits into a single logical one. The implications of this overhead project are profound, especially for chip design. Unlike classical bits, which are inherently stable and can be copied or stored without degradation, qubits are fragile. They exist in superposition only temporarily and are overly sensitive to disturbances from their environment. A stray photon, a lattice defect, or even a thermal fluctuation can destroy coherence. As a result, quantum chips must allocate enormous resources to shielding, correcting, and isolating qubits.
Understanding the 1000 to 1 Problem
The most common estimate cited by hardware developers is that about 1,000 physical qubits are needed to support a single usable, or logical, qubit. This number isn’t fixed. It varies by hardware platform, error rate, and correction code, but it reflects the fundamental difficulty of maintaining quantum coherence over time. “Noise in current qubits means that many physical qubits are needed to make up a single usable one. The ratio today is about 1000:1, but that number varies according to the noise level of the physical cubits,” Erik Hosler explains.
This ratio has a cascading impact. If a commercial quantum computer needs 1,000 logical qubits to tackle a meaningful chemistry or optimization problem, the total number of physical qubits required could approach one million. That kind of scaling presents serious constraints on layout, interconnect, cooling, and fabrication strategy.
Space, Power, and Routing Overhead
The first implication of this ratio is geometric. Packing one million qubits onto a single chip is not just a matter of miniaturization. Each qubit must be isolated enough to avoid crosstalk but connected enough to participate in entangled operations. Routing signals between them, whether electrical, optical, or microwave, requires a high-density interconnect scheme.
Designers are exploring various tiling architectures to solve this, including two-dimensional arrays with nearest-neighbor coupling, modular clusters with optical links, and hierarchical grids. Each of these choices affects how qubits are addressed, how errors are propagated, and how calibration is managed.
Then there is power. Each control line, amplifier, and signal path consumes energy. When scaled to thousands or millions of units, power delivery and thermal dissipation become nontrivial. Even with cryogenic amplifiers and low-power microwave drivers, maintaining signal integrity at scale remains a core design obstacle.
Yield and Fabrication Complexity
A second consequence of the 1000 to 1 ratio is yield. Classical semiconductor manufacturing already contends with defects per wafer and process variability. In a quantum context, even small variations in junction width, oxide thickness, or etch depth can lead to nonfunctioning qubits.
It raises the bar for lithographic precision and metrology. Chipmakers must characterize and calibrate each qubit individually, mapping out its error rates and tuning parameters. The more physical qubits are needed, the more this characterization effort scales.
In some cases, redundancy can help. Engineers may include spare qubit regions on-chip, routing around dead or unreliable units. But this strategy introduces more complexity into layout and verification, and it does not eliminate the root problem.
Co-Designing Chips and Codes
One emerging trend is the co-design of hardware and error correction. Rather than developing chips first and applying generic correction codes afterward, some teams are creating error-correcting architectures tailored to the physical constraints of their platform.
For instance, surface codes have become popular because they require only local connectivity and tolerate a high degree of physical qubit noise. But newer schemes like LDPC codes, cat codes, and bosonic encodings offer different trade-offs between space, depth, and fault tolerance.
By designing chips and codes together, developers can optimize placement, routing, and control electronics. They can also reduce the number of redundant physical qubits needed, shrinking the 1000:1 ratio over time.
Implications for Lithography and Metrology
The SPIE panel highlighted that conventional lithography processes are being pushed to their limits by quantum requirements. Tighter line edge roughness, phase control, and pattern fidelity are needed to fabricate repeatable, high-performing qubits.
Advanced metrology tools now analyze not just critical dimensions but electromagnetic behavior, noise susceptibility, and thermal stability. These metrics feed into mask tuning and etch compensation workflows, creating a tighter feedback loop between design and fab.
Some developers are investigating new resist chemistries and etch profiles that reduce variability at the atomic scale. Others are exploring litho-friendly qubit designs that are more tolerant of process drift. All these efforts aim to improve yield without sacrificing coherence.
Modularization and Heterogeneous Stacking
To manage the footprint of a million-qubit system, some teams are looking at modular chiplets. Each module contains a few thousand qubits and can be evaluated independently before being connected optically or electronically to form a larger machine.
This modular approach is borrowed from classical system-on-chip and multi-chip packaging techniques. It allows for defect isolation, asynchronous scaling, and thermal compartmentalization. It also makes it easier to upgrade parts of the system without redesigning the entire layout.
Vertical integration is another option. Using through-silicon vias or superconducting interposers, developers can stack quantum layers with control and readout electronics. This layering helps reduce wire length and surface area while increasing interconnect density.
Building with Today’s Limits in Mind
For now, chip architects must work within the constraints imposed by noisy hardware. That means planning for redundancy, accommodating calibration, and tolerating defects. It means partnering closely with fabs to control variability and testing strategies that maximize usable yield.
It also means designing for flexibility. Layouts that can accommodate different codes, reroute signals, or substitute components will fare better in this dynamic environment. Quantum design is not static, but a field shaped by physics, engineering, and manufacturing simultaneously.
The 1000 to 1 qubit ratio may seem discouraging, but it is also an invitation to innovate in chip architecture, push the boundaries of lithography, and develop smarter, more efficient systems. Those who meet that challenge will help shape the first generation of practical quantum computers.
